1. Field of the Invention
The present invention relates to a synchronous type semiconductor memory device, and more particularly, to a synchronous semiconductor memory device that receives an external signal in synchronization with an externally applied clock signal.
2. Description of the Background Art
Although a dynamic random access memory (referred to as DRAM hereinafter) employed used as a main memory is increased in speed, the operating rate still does not yet comply with the improvement in the operating rate of a microprocessor (MPU).
The access time and cycle time of a DRAM becomes the bottleneck to prevent improvement of the entire system performance. A synchronous semiconductor memory device (referred to as SDRAM hereinafter) that operates in synchronization with an externally applied clock signal is proposed as the main memory for the recent high speed MPU.
In an SDRAM, successive access specification set forth in the following in synchronization with a system clock which is an external clock signal is proposed.
A typical operation for meeting the high speed access specification of a conventional SDRAM will be described hereinafter with reference to the timing charts of FIGS. 13A-13F.
In FIGS. 13A-13F, the writing or reading operation of data of 8 successive bits (a total of 64 bits by 8.times.8) in an SDRAM that allows input and output of 8-bit data (byte data) through data input/output terminals DQ0-DQ7 is shown. The number of bits of data read out continuously is called "burst length". In an SDRAM, the burst length can be modified by a mode register.
As shown in FIGS. 13A-13F, an external control signal (for example, a row address strobe signal /RAS, a column address strobe signal /CAS, an address signal Add, and the like) is received at a rising edge of an externally applied clock signal ext.CLK in an SDRAM. Address signal Add is applied having a row address signal X and a column address signal Y multiplexed in a time divisional manner. When row address strobe signal /RAS is in an active state of L (logical low) at a rising edge of external clock signal ext.CLK, the current address signal Add is received as row address signal X.
When column address strobe signal /CAS is in an active state of an L level at a rising edge of external clock signal ext.CLK, the current address signal Add is input as a column address Y. A select operation of a row and a column is carried out in an SDRAM according to the received row address signal (Xa in FIG. 13E) and column address signal (Yb in FIG. 13E).
At an elapse of a predetermined clock period (3 clock cycles in FIG. 13A) from a fall of row address strobe signal /RAS to an L level, the first 8-bit data is output.
Data is output in response to a rise of external clock signal ext.CLK thereafter.
In a writing operation, a row address signal is input in a manner similar to that of the readout operation (Xc in FIG. 13E). When column address strobe signal /CAS and write enable signal /WE both are at an L level of an active state at a rising edge of external clock signal ext.CLK, a column address signal (Yd in FIG. 13E) is input, and the currently applied data (d0 in FIG. 13F) is taken as the first write data.
In response to a fall of row address strobe signal /RAS and column address strobe signal /CAS, a row and column select operation is carried out in the SDRAM. Input data d1, . . . , d7 are sequentially received in synchronization with external clock signal ext. CLK. The input data is sequentially written into a memory cell.
In contrast to a conventional DRAM that receives an address signal, input data, and the like in synchronization with an external control signal (row address strobe signal /RAS and column address strobe signal /CAS), an external signal (row address strobe signal /RAS, column address strobe signal /CAS, address signal Add, input data, and the like) is received at a rising edge of an externally applied clock signal ext.CLK in an SDRAM.
The successive access time can be speeded if writing and reading of continuous data can be effected in synchronization with an external clock signal.
In accordance with a MPU of a higher rate, the problem of improving the speed of an internal clock signal has become in inevitable from the standpoint of the entire system performance. Therefore, an internal clock generation circuit is proposed directed to generating an internal clock signal in synchronization with a received external clock signal ext.CLK. An internal clock generation circuit is disclosed in, for example, "PHASE COMPARATOR AND PLL CIRCUIT" (Japanese Patent Laying-Open No. 7-273645), and "INTEGRATING PHASE DETECTOR" (U.S. Pat. No. 5,252,865).
A delay locked loop (referred to as DLL circuit hereinafter) which is an example of an internal clock signal generation circuit incorporated in a conventional SDRAM will be described hereinafter with reference to FIG. 14.
Referring to FIG. 14, a conventional DLL circuit 900 includes a clock buffer 2, a delay line 4, shift register 6, a delay circuit 8 and a phase comparator 14.
Clock buffer 2 receives an externally applied clock signal (referred to as external clock signal CLK0 hereinafter) and provides a clock signal ECLK. Delay line 4 delays clock signal ECLK and provides a clock signal (referred to as internal clock signal CLK1 hereinafter). Delay circuit 8 delays internal clock signal CLK1 for providing a clock signal RCLK. Phase comparator 14 compares the phases of clock signal ECLK received via a signal line A1 and clock signal RCLK received via a signal line A2 to alter the state of shift register 6 according to the comparison result. Shift register 6 responds to an output of phase comparator 14 to alter the delay time of delay line 4.
More specifically, when clock signal RCLK corresponding to internal clock signal CLK1 is behind clock signal ECLK corresponding to external clock signal CLK0, the delay time of delay line 4 is shortened. When clock signal RCLK is ahead of clock signal ECLK in phase, the delay time of delay line 4 is lengthened. As a result, an internal clock signal CLK1 in phase-synchronization with external clock signal CLK0 is output.
The structure of conventional phase comparator 14 will be described briefly hereinafter with reference to FIG. 15.
Referring to FIG. 15, phase comparator 14 includes delay circuits 90, 91, 92 and 93, inverter circuits 73, 74, 75, 76, and 77, AND circuits 79 and 80, latch circuits 81, 82, 83, 84, 85, and 86, and MOS transistors N12, N13, N14, N15, N16 and N17.
Delay circuit 90 delays the received signal of an input node Z60 and provides the delayed signal (referred to as clock signal EC hereinafter). Delay circuit 91 delays the received signal of an input node Z65 and provides the delayed signal. Delay circuit 92 delays the received signal from delay circuit 91 and provides the delayed signal. Delay circuit 93 delays the received signal of input node Z65 and provides the delayed signal.
Input node Z60 is connected to signal line Al of FIG. 14. Input node Z65 is connected to signal line A2 of FIG. 14
Inverter circuits 73, 74, 75 and 76 are connected in series. Inverter circuit 73 receives an input clock signal EC. Inverter circuit 76 has its output node connected to a first input node of AND circuit 79 and to a first input node of AND circuit 80.
MOS transistor N12, latch circuit 81, MOS transistor N15 and latch circuit 84 are connected in series between the output node of delay circuit 92 and a second input node of AND circuit 79. MOS transistor N13, latch circuit 82, MOS transistor N16 and latch circuit 85 are connected in series between delay circuit 93 and a third input node of AND circuit 79. Inverter circuit 77 is connected between latch circuit 85 and a second input node of AND circuit 80. MOS transistor N14, latch circuit 83, MOS transistor N17 and latch circuit 86 are connected in series between input node Z65 and a third input node of AND circuit 80.
MOS transistors N12, N13 and N14 have respective gate electrodes connected to the output node of inverter circuit 73. MOS transistors N15, N16 and N17 have respective gate electrodes connected to the output node of inverter circuit 74.
Each of latch circuits 81, 82, 83, 84, 85 and 86 includes inverter circuits 95 and 96.
Here, the signal applied to the second input node of AND circuit 79 is referred to as signal C. The signal applied to inverter circuit 77 is referred to as signal B. The signal applied to the third input node of AND circuit 80 is referred to as signal A.
In phase comparator 14 shown in FIG. 15, signals A, B and C are altered according to the phase difference between the signal received at input node Z60 and the signal received at input node Z65 at the trigger of clock signal EC.
More specifically, when the signal received at input node Z60 is ahead of the signal received at input node Z65, signal A attains an H level, and signals B and C attain an L level. As a result, a DOWN signal of an H level is output from AND circuit 79.
When the signal received at input node Z65 is behind the signal received at input node Z60, signals A, B and C all attain an H level, whereby an UP signal of an H level is output from AND circuit 80.
The phases between an external clock signal and a generated internal clock signal must be compared in order to generate an internal clock signal that is in phase-synchronization with an external clock signal.
However, the conventional phase comparator had the problem that the phase comparison precision is limited due to the switching time of the transistor which is a constitutional element, the inversion time of the latch, and also by difference in the load capacitance.
Therefore, a stable high speed operation cannot be realized in an SRAM incorporating an internal clock generation circuit with such a phase comparator.